Contents

<!– Generated by hand for SushiDSP phase D6a. –>

ts_clip

TS808 clipping stage: input coupling, ideal non-inverting op-amp with the drive-dependent feedback network and the antiparallel silicon diode pair.

Status: simulated. Commit 2bdbf91 ran this block and committed its CSVs.

LTspice version: LTspice 24, the only detail 2bdbf91 records; the exact build is not recorded by that commit.

How the schematic is written

ts_clip.asc carries the whole circuit as SPICE directive text on the sheet rather than as placed symbols with wires. Directive lines are netlisted verbatim by LTspice, so node names are explicit and the netlist cannot depend on symbol pin geometry that could not be checked without running the tool.

Analyses

Both analysis lines live on the sheet as comments and tools/spice/export.py enables exactly one of them per run:

  • ;ac dec 40 10 20k
  • ;tran 0 40m 20m 1u (40 ms run, the last 20 ms saved as steady state)

.options plotwinsize=0 keeps the raw file uncompressed.

Probe and stimulus

  • Probed node: out (the op-amp output).
  • Input node: src
  • Source: V1 src 0 SINE(0 {AMP} 1k) AC 1
  • Input level(s): AMP = 100 mV fixed (this block steps Drive instead).

Stepped control

.step param DRIVE list 0.1 0.5 0.9

DRIVE is the normalised 500 kΩ drive-pot fraction, applied linearly. D6c applies an audio-taper law to the normalised parameter before the pot enters the circuit; the SPICE reference steps the post-taper fraction directly, so the C++ side must compare at matching post-taper values, not matching knob positions.

Components

Ref Value Nodes Spec reference
V1 SINE(0 {AMP} 1k) AC 1 src - 0 D6c stimulus
Cin 1 uF src - in D6c 1 uF input cap
Rin 510 kΩ in - 0 D6c 510 kΩ (~0.31 Hz corner)
Eop gain 1e6 out - 0, sense (in, inv) D6c ideal op-amp
Rf {51k + DRIVE*500k} out - inv D6c Rf = 51 kΩ + Drive*500 kΩ
Cf 51 pF out - inv D6c 51 pF across the feedback
D1 D1N914 out -> inv D6c antiparallel diode pair
D2 D1N914 inv -> out D6c antiparallel diode pair
Rg 4.7 kΩ inv - gnd1 D6c 4.7 kΩ to ground leg
Cg 47 nF gnd1 - 0 D6c 47 nF to ground leg

Judgment calls

  • The TS808’s real 4.5 V bias rail is omitted; the ideal op-amp is referenced to ground and the whole stage runs bipolar. Signal behaviour is identical and it removes a large DC transient from the start of every run.
  • The unity input buffer that D6c models as linear is omitted for the same reason: it contributes nothing at these impedances.
  • Eop is an ideal VCVS with a gain of 1e6 and no pole, matching D6c’s Vout = Vin + i_f*Zf statement exactly.
  • .include ../models/d1n914.sub pulls in the .model D1N914 line (D6b.3: Is = 2.52 nA, n = 1.752).